
IDT82V3255
WAN PLL
Functional Block Diagram
11
December 3, 2008
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
EX_
SY
NC
3
Mo
ni
to
rs
T0
PF
D
&LP
F
Di
vid
er
T4
P
FD
&LP
F
Div
ide
r
AP
LL
Mic
rop
ro
ce
ss
or
In
te
rfa
ce
JT
AG
PB
O
Ph
as
eO
ffs
et
77
.7
6M
H
z
T4
AP
LL
T0
AP
LL
Di
vi
de
r
OU
T1
OU
T3
MUX
OU
T2
OU
T7
MUX
T4
APL
L
MUX
T0
APL
L
MUX
T4
In
pu
t
Sel
ect
or
T0
In
pu
t
Se
le
ct
or
OS
C
I
77
.7
6M
H
z
16
E1
/1
6T
1
12
E1
/2
4T
1/
E3
/T
3
16
E1
/1
6T
1
12
E1
/2
4T
1/
E3
/T
3
Aut
o
Di
vi
de
r
Aut
o
Di
vid
er
10
T0
DPLL
T4
D
PLL
Input
IN1
_CM
OS
IN
1_
D
IF
F
EX
_S
YNC
1
IN2
_C
M
OS
IN2_
DIFF
EX
_S
YNC
2
IN
3_C
MO
S
FR
SYN
C_
8K
MF
R
SYN
C_
2K
O
utput
G
SM
/G
PS
/16E
1/16T
1
T0
77.7
6
M
H
z
T0
8
kH
z
G
SM/O
BS
AI/
16E1/
16T
1
8k
D
ivi
de
r
Input
Pr
e-
Di
vi
der
Pr
io
rity
Input
Pr
e-
Di
vi
der
Pr
io
rity
Input
Pr
e-
Di
vi
der
Pr
io
rity
Input
Pr
e-
Di
vi
der
Pr
io
rity
Input
Pr
e-
Di
vi
der
Pr
io
rity
Di
vi
de
r
EX
_S
YNC1
EX
_S
YNC2
EX
_S
YNC3